1. Field of the Invention
The instant disclosure relates to a static random access memory cell; in particular, to a 6T static random access memory cell, array, and memory thereof.
2. Description of Related Art
In order to reduce required power consumption, minimizing the size of the integrated circuit memory devices in semiconductors is still the direction to strive for. Memory devices in semiconductors include static random access memory (SRAM) and dynamic random access memory (DRAM). DRAM memory cells only have one transistor and a capacitor, which provides high integrability. However, since DRAM requirement for continuous replacement, high power consumption and slow speed makes DRAM a memory choice limited to mostly computer memories. On the other hand, SRAM cells have bistability, which means with the appropriate power, SRAM can continuously maintain the original state. SRAM can operate in high speed under low power consumption such that computers mostly use a lot of cache SRAM. Other applications include embedded memory, and network device memory.
Conventional structures of common SRAM cells include six transistors (6T) having 6 MOS transistors. Please refer to FIG. 1 as a circuit diagram of a conventional 6T static random access memory cell. The conventional 6T static random access memory cell 1 includes a first inverter 11, a second inverter 12, a first access transistor M5, and a second access transistor M6. The first inverter 11 includes a first pull-up transistor M1 and a first pull-down transistor M3, whereas the second inverter 12 includes a second pull-up transistor M2 and a second pull-down transistor M4. The first pull-up transistor M1 has a source terminal and the second pull-up transistor M2 has a source terminal cooperatively coupled to a supply voltage VDD. The first pull-down transistor M3 has a source terminal and the second pull-down transistor M4 has a source terminal cooperatively coupled to a low supply voltage VSS. The first pull-down transistor M3 has a drain terminal and the first pull-up transistor M1 has a drain terminal cooperatively couple to form a first node Q. The second pull-down transistor M4 has a drain terminal and the second pull-up transistor M2 has a drain terminal cooperatively couple to form a second node QB.
The first access transistor M5 has a gate terminal coupled to a word line WL, a source terminal coupled to the first node Q, and a drain terminal coupled to a first bit line BL. The second access transistor M6 has a gate terminal coupled to the word line WL, a source terminal coupled to the second node QB, and a drain terminal coupled to a second bit line BLB.
Please refer to FIGS. 1 and 2. FIG. 2 is a signal diagram of the conventional 6T static random access memory cell while data are being written thereon. Generally, a conventional 6T static random access memory cell 1 must fix the first bit line BL and the second bit line BLB to a group of fixed voltage when data are being written, such that data stored in the first node Q and the second node QB are forced to flip.
Please refer to FIGS. 1 and 3. FIG. 3 is a signal diagram of the conventional 6T static random access memory cell while data are being read therefrom. A conventional 6T static random access memory cell 1 must pull the electric potential of word line WL to “1” (refer to T3-T4 interval as shown in FIG. 3) when data is being read, which is different from writing, and the electric potential of the first bit line BL must pull up and equal to the second bit line BLB before the electric potential of the word line WL pulls up to “1”, the first bit line BL and the second bit line BLB must have equal electric potentials such as “1” as shown in FIG. 3. When the first bit line BL is equal to the second bit line BLB and floating, the word line WL then provides ON signals. The conventional 6T static random access memory cell uses the storage values of the first node Q and the second node QB and, via the first access transistor M5 and the second access transistor M6, and generates charge sharing and voltage division respectively with the first bit line BL and the second bit line BLB, such that difference in electric potential is induced between the first bit line BL and the second bit line BLB. As shown in FIG. 3, electric potential signal of the first bit line BL is affected, thus voltage is reduced. Successively, external signal amplifier (not illustrated) amplifies differences in signals and read out voltage value as “0” or “1”.
However, when the conventional 6T static random access memory cell 1 is reading data, the first node Q and the second node QB are prone to mutually interfere which prevent the stored values from smoothly flipping. As shown in FIG. 2, it is impossible to flip the voltage values of the first and second node Q, QB such that writing fails during time intervals T1 and T2. Moreover, as shown in FIG. 3, when the conventional 6T static random access memory cell 1 is reading, the voltage values of the first and second node Q, QB will mutually interfere in time intervals T3 and T4 due to voltage division. In turn, unexpected flipping of originally stored data might occur when data is being read, thus providing erroneous data. As a result, there is still much room for improvement in SRAM design.
To address the above issues, the inventor strives via associated experience and research to present the instant disclosure, which can effectively improve the limitation described above.